The cache of Cortex-A7 is only enabled if the SMP bit is set, but the
SMP bit of V3s is wrongly left unset, because I thought that it's not
SMP-capable.
Fix this.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
After a fifo length of data is sent to tx fifo, the tx buffer should be
offseted.
Do this offset after the transfer.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Allwinner V3s SoC has a SPI controller which is the same as the
controllers in H3 SoC.
Add a device tree node for it, so that it can be usable.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Introduces SPI registers for sun6i/sun8i/sun9i/sun50i by adding struct
sunxi_spi_regs and flags.
Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
Added missing AHB_GATE_OFFSET_SPIx defines to enable/disable clock gating for
SPI on the sun6i and sun9i platforms.
Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
This is needed for HDMI support, which will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[Icenowy: renamed back lcd0_ch0_clk_cfg, add PLL3 for DE2 on V3s,
and add CONFIG_SUNXI_DE2]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
USB OTG on V3s SoC seems to need the USB OTG clock gate to be passed and
the reset to be deasserted before boot, otherwise it won't work in
Linux.
Add this quirk.
Also add a generic quirk framework in sunxi's clock initialization code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
V3s devices won't have enough memory to load U-Boot binary at
0x4a000000, and they do not have enough memory to reserve 64MiB for
malloc() (it has only 64MiB at all!)
Change the DRAM mapping for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
As we have now V3s support in board code, the V3s DTSI file should also
be added.
Add also some CCU include headers to satisfy the DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
H3-like DRAM controller needs some special code to operate a DDR2 DRAM
chip. Add the logic to probe such a chip.
As there's no commercial boards available now with H3 and DDR2 DRAM, the
patch is developed and tested on a V3s chip, which has in-package DDR2
DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
To use driver-model adds the pmic node for max8998.
This is used as kerel device-tree in Linux.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add the max8998 controller for Driver model.
Samsung S5P series are using max8998 pmic controller.
In future, it should be supported the regulator framework.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the entire spear_sdhci.c file.
There is no use case. This is dead codes.
Also there is no place to call "spear_sdhci_init()" anywhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fix the MMU mapping for A8K device family:
- Separate A7K and A8K memory mappings
- Fix memory regions by including IO mapping for all
3 PCIe interfaces existing on each connected CP110 controller
Add A8K memory mapping documentation with all regions
configured by Marvell ATF.
Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"<chip>-l2-cache-controller" and "cache" as values.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
H3 SID controller has some bug, which makes the initial SID value at
SUNXI_SID_BASE wrong when boot.
Change the SID retrieve code to call the SID Controller directly on H3,
which can get the correct value, and also fix the SID value at
SUNXI_SID_BASE, so that it can be used by further operations.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
nearology
Icenowy Zheng