sunxi: add SPI driver for Allwinner devices (sunxi)
Implements a driver model SPI driver for Allwinner devices (sunxi). Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
This commit is contained in:
S.J.R. van Schaik
committed by
Icenowy Zheng
Icenowy Zheng
parent
f335000967
commit
ae851665c7
@@ -124,6 +124,11 @@ config SANDBOX_SPI
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};
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};
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config SUNXI_SPI
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bool "Allwinner SPI driver"
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help
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Enable the Allwinner SPI driver.
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config TEGRA114_SPI
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bool "nVidia Tegra114 SPI driver"
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help
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@@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
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obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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obj-$(CONFIG_SUNXI_SPI) += sunxi_spi.o
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obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
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@@ -0,0 +1,355 @@
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/*
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* (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
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* S.J.R. van Schaik <stephan@whiteboxsystems.nl>
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* M.B.W. Wajer <merlijn@whiteboxsystems.nl>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <spi.h>
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#include <asm/bitops.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/spi.h>
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#define SUNXI_SPI_MAX_RATE (24 * 1000 * 1000)
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#define SUNXI_SPI_MIN_RATE (3 * 1000)
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struct sunxi_spi_platdata {
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struct sunxi_spi_regs *regs;
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unsigned int activate_delay_us;
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unsigned int deactivate_delay_us;
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uint32_t freq;
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};
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struct sunxi_spi_priv {
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struct sunxi_spi_regs *regs;
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unsigned int max_freq;
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unsigned int last_transaction_us;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static void sunxi_spi_setup_pinmux(unsigned int pin_func)
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{
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unsigned int pin;
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for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
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sunxi_gpio_set_cfgpin(pin, pin_func);
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if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) {
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sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_func);
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} else {
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sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_func);
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}
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}
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static void sunxi_spi_enable_clock(struct udevice *bus)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg * const)SUNXI_CCM_BASE;
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
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defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
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setbits_le32(&ccm->ahb_reset0_cfg,
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(1 << AHB_GATE_OFFSET_SPI0));
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#endif
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
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writel((1 << 31), &ccm->spi0_clk_cfg);
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}
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static void sunxi_spi_disable_clock(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg * const)SUNXI_CCM_BASE;
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writel(0, &ccm->spi0_clk_cfg);
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clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
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defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
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clrbits_le32(&ccm->ahb_reset0_cfg,
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(1 << AHB_GATE_OFFSET_SPI0));
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#endif
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}
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static void sunxi_spi_cs_activate(struct udevice *dev, unsigned int cs)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_platdata *plat = dev_get_platdata(bus);
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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uint32_t reg;
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/* If it is too soon to perform another transaction, wait. */
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if (plat->deactivate_delay_us && priv->last_transaction_us) {
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unsigned int delay_us;
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < plat->deactivate_delay_us)
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udelay(plat->deactivate_delay_us - delay_us);
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}
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debug("%s: activate cs: %u, bus: '%s'\n", __func__, cs, bus->name);
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reg = readl(&priv->regs->xfer_ctl);
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reg &= ~(SUNXI_SPI_CTL_CS_MASK | SUNXI_SPI_CTL_CS_LEVEL);
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reg |= SUNXI_SPI_CTL_CS(cs);
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writel(reg, &priv->regs->xfer_ctl);
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if (plat->activate_delay_us)
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udelay(plat->activate_delay_us);
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}
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static void sunxi_spi_cs_deactivate(struct udevice *dev, unsigned int cs)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_platdata *plat = dev_get_platdata(bus);
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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uint32_t reg;
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debug("%s: deactivate cs: %u, bus: '%s'\n", __func__, cs, bus->name);
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reg = readl(&priv->regs->xfer_ctl);
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reg &= ~SUNXI_SPI_CTL_CS_MASK;
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reg |= SUNXI_SPI_CTL_CS_LEVEL;
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writel(reg, &priv->regs->xfer_ctl);
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/*
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* Remember the time of this transaction so that we can honour the bus
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* delay.
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*/
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if (plat->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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}
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static int sunxi_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct sunxi_spi_platdata *plat = dev_get_platdata(bus);
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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plat->regs = (struct sunxi_spi_regs *)dev_get_addr(bus);
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plat->activate_delay_us = fdtdec_get_int(
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blob, node, "spi-activate_delay", 0);
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plat->deactivate_delay_us = fdtdec_get_int(
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blob, node, "spi-deactivate-delay", 0);
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debug("%s: regs=%p, activate-delay=%u, deactivate-delay=%u\n",
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__func__, plat->regs, plat->activate_delay_us,
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plat->deactivate_delay_us);
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return 0;
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}
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static int sunxi_spi_probe(struct udevice *bus)
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{
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struct sunxi_spi_platdata *plat = dev_get_platdata(bus);
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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debug("%s: probe\n", __func__);
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priv->regs = plat->regs;
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priv->last_transaction_us = timer_get_us();
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return 0;
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}
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static int sunxi_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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unsigned int pin_func = SUNXI_GPC_SPI0;
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debug("%s: claiming bus\n", __func__);
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if (IS_ENABLED(CONFIG_MACH_SUN50I))
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pin_func = SUN50I_GPC_SPI0;
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sunxi_spi_setup_pinmux(pin_func);
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sunxi_spi_enable_clock(bus);
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setbits_le32(&priv->regs->glb_ctl, SUNXI_SPI_CTL_MASTER |
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SUNXI_SPI_CTL_ENABLE | SUNXI_SPI_CTL_TP | SUNXI_SPI_CTL_SRST);
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if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
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while (readl(&priv->regs->glb_ctl) & SUNXI_SPI_CTL_SRST)
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;
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setbits_le32(&priv->regs->xfer_ctl, SUNXI_SPI_CTL_CS_MANUAL |
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SUNXI_SPI_CTL_CS_LEVEL);
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setbits_le32(&priv->regs->fifo_ctl, SUNXI_SPI_CTL_RF_RST |
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SUNXI_SPI_CTL_TF_RST);
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return 0;
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}
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static int sunxi_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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debug("%s: releasing bus\n", __func__);
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clrbits_le32(&priv->regs->glb_ctl, SUNXI_SPI_CTL_MASTER |
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SUNXI_SPI_CTL_ENABLE);
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sunxi_spi_disable_clock();
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return 0;
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}
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static void sunxi_spi_write(struct udevice *dev, const char *tx_buf,
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size_t nbytes)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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size_t i;
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char byte;
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if (!tx_buf)
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nbytes = 0;
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writel(SUNXI_SPI_XMIT_CNT(nbytes), &priv->regs->xmit_cnt);
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if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
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writel(SUNXI_SPI_BURST_CNT(nbytes), &priv->regs->burst_ctl);
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for (i = 0; i < nbytes; ++i) {
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byte = tx_buf ? *tx_buf++ : 0;
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writeb(byte, &priv->regs->tx_data);
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}
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}
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static int sunxi_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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const char *tx_buf = dout;
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char *rx_buf = din;
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size_t len = bitlen / 8;
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size_t i, nbytes;
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char byte;
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if (bitlen % 8) {
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debug("%s: non byte-aligned SPI transfer.\n", __func__);
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return -1;
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}
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if (flags & SPI_XFER_BEGIN)
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sunxi_spi_cs_activate(dev, slave_plat->cs);
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while (len) {
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nbytes = min(len, (size_t)64 - 1);
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writel(SUNXI_SPI_BURST_CNT(nbytes), &priv->regs->burst_cnt);
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sunxi_spi_write(dev, tx_buf, nbytes);
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setbits_le32(&priv->regs->xfer_ctl, SUNXI_SPI_CTL_XCH);
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while (((readl(&priv->regs->fifo_sta) &
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SUNXI_SPI_FIFO_RF_CNT_MASK) >>
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SUNXI_SPI_FIFO_RF_CNT_BITS) < nbytes)
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;
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for (i = 0; i < nbytes; ++i) {
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byte = readb(&priv->regs->rx_data);
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if (rx_buf)
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*rx_buf++ = byte;
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}
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len -= nbytes;
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}
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if (flags & SPI_XFER_END)
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sunxi_spi_cs_deactivate(dev, slave_plat->cs);
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return 0;
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}
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static int sunxi_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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unsigned int div;
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uint32_t reg;
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speed = min(speed, (unsigned int)SUNXI_SPI_MAX_RATE);
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speed = max((unsigned int)SUNXI_SPI_MIN_RATE, speed);
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div = SUNXI_SPI_MAX_RATE / (2 * speed);
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if (div <= (SUNXI_SPI_CLK_CTL_CDR2_MASK + 1)) {
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if (div > 0)
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div--;
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reg = SUNXI_SPI_CLK_CTL_CDR2(div) | SUNXI_SPI_CLK_CTL_DRS;
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} else {
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div = __ilog2(SUNXI_SPI_MAX_RATE) - __ilog2(speed);
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reg = SUNXI_SPI_CLK_CTL_CDR1(div);
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}
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writel(reg, &priv->regs->clk_ctl);
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debug("%s: speed=%u\n", __func__, speed);
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return 0;
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}
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static int sunxi_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct sunxi_spi_priv *priv = dev_get_priv(bus);
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uint32_t reg;
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reg = readl(&priv->regs->xfer_ctl);
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reg &= ~(SUNXI_SPI_CTL_CPOL | SUNXI_SPI_CTL_CPHA |
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SUNXI_SPI_CTL_CS_ACTIVE_LOW);
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if (mode & SPI_CPOL)
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reg |= SUNXI_SPI_CTL_CPOL;
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if (mode & SPI_CPHA)
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reg |= SUNXI_SPI_CTL_CPHA;
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if (!(mode & SPI_CS_HIGH))
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reg |= SUNXI_SPI_CTL_CS_ACTIVE_LOW;
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writel(reg, &priv->regs->xfer_ctl);
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debug("%s: mode=%d\n", __func__, mode);
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return 0;
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}
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static const struct dm_spi_ops sunxi_spi_ops = {
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.claim_bus = sunxi_spi_claim_bus,
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.release_bus = sunxi_spi_release_bus,
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.xfer = sunxi_spi_xfer,
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.set_speed = sunxi_spi_set_speed,
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.set_mode = sunxi_spi_set_mode,
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};
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static const struct udevice_id sunxi_spi_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-spi" },
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{ .compatible = "allwinner,sun6i-a31-spi" },
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{ .compatible = "allwinner,sun8i-h3-spi" },
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{ .compatible = "allwinner,sun50i-a64-spi" },
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{ }
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};
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U_BOOT_DRIVER(sunxi_spi) = {
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.name = "sunxi_spi",
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.id = UCLASS_SPI,
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.of_match = sunxi_spi_ids,
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.ops = &sunxi_spi_ops,
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.ofdata_to_platdata = sunxi_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct sunxi_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct sunxi_spi_priv),
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.probe = sunxi_spi_probe,
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};
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