Beniamino Galvani
bfcef28ae4
This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <dm/platdata.h>
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#include <phy.h>
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int board_init(void)
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{
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return 0;
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}
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static const struct eth_pdata gxbb_eth_pdata = {
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.iobase = GXBB_ETH_BASE,
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.phy_interface = PHY_INTERFACE_MODE_RGMII,
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};
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U_BOOT_DEVICE(meson_eth) = {
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.name = "eth_designware",
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.platdata = &gxbb_eth_pdata,
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};
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int misc_init_r(void)
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{
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/* Select Ethernet function */
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setbits_le32(GXBB_PINMUX(6), 0x3fff);
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/* Set RGMII mode */
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setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
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GXBB_ETH_REG_0_TX_PHASE(1) |
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GXBB_ETH_REG_0_TX_RATIO(4) |
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GXBB_ETH_REG_0_PHY_CLK_EN |
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GXBB_ETH_REG_0_CLK_EN);
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/* Enable power and clock gate */
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setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
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clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
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/* Reset PHY on GPIOZ_14 */
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clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
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clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
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mdelay(10);
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setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
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return 0;
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}
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