Peng Fan a2c74aaf51 imx: mx6ul select SYS_L2CACHE_OFF ...

i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

2015-08-02 11:05:08 +02:00

..

arc

arc: significant cache rework

2015-07-01 17:17:27 +03:00

arm

imx: mx6ul select SYS_L2CACHE_OFF

2015-08-02 11:05:08 +02:00

avr32

avr32: delete ancient board.c

2015-06-10 14:03:26 +02:00

blackfin

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

m68k

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

microblaze

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

mips

MIPS: change 'extern inline' to 'static inline'

2015-07-02 11:29:33 +02:00

nds32

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

nios2

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

openrisc

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

powerpc

powerpc: gitignore: ignore PowerPC DTBs

2015-05-28 08:18:20 -04:00

sandbox

sandbox: Add an implementation for cleanup_before_linux_select()

2015-06-10 19:26:54 -06:00

sh

Move default y configs out of arch/board Kconfig

2015-06-25 22:17:55 -04:00

sparc

arch: Make board selection choices optional

2015-05-12 18:10:02 -04:00

x86

dm: x86: baytrail: Correct PCI region 3 when driver model is used

2015-07-14 18:03:19 -06:00

.gitignore

…

Kconfig

ARM: disable HAVE_PRIVATE_LIBGCC for ARM64

2015-07-07 11:39:51 +02:00