York Sun dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378 ...

Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>

2015-01-23 22:29:13 -06:00

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fsl

arm/ls1021a: Add workaround for DDR erratum A008378

2015-01-23 22:29:13 -06:00