XPedite5500 board support
Initial support for Extreme Engineering Solutions XPedite5500 - a P2020-based PMC/XMC single board computer. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
John Schmoller
committed by
Kumar Gala
Kumar Gala
parent
66a8b440af
commit
bfe18815e8
@@ -32,7 +32,9 @@ LIB = $(obj)lib$(VENDOR).a
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
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COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
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COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
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COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
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COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
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COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
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@@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
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if (in_be32(&gur->gpporcr) & 0x10000)
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return 66666666;
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else
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#ifdef CONFIG_P2020
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return 100000000;
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#else
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return 50000000;
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#endif
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}
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#ifdef CONFIG_MPC85xx
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@@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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#ifdef CONFIG_P2020
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if (in_be32(&gur->gpporcr) & 0x20000)
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return 66666666;
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else
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return 100000000;
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#else
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return 66666666;
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#endif
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}
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#endif
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@@ -0,0 +1,39 @@
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#
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# Copyright 2007-2008 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@@ -0,0 +1,165 @@
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/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr3_spd_eeprom_t));
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}
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0 && i == 0)
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i2c_address = SPD_EEPROM_ADDRESS1;
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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/*
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* There are traditionally three board-specific SDRAM timing parameters
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* which must be calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 3.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* ====== XPedite550x DDR3-800 read delay calculations ======
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*
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* The P2020 processor provides an autoleveling option. Setting CPO to
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* 0x1f enables this auto configuration.
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*/
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typedef struct {
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unsigned short datarate_mhz_low;
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unsigned short datarate_mhz_high;
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unsigned char clk_adjust;
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unsigned char cpo;
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} board_specific_parameters_t;
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const board_specific_parameters_t board_specific_parameters[][20] = {
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{
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/* Controller 0 */
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{
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/* DDR3-600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo = 31,
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},
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{
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/* DDR3-800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo = 31,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/*
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* Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i&1) { /* odd CS */
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 0;
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} else { /* even CS */
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if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 4;
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} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
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popts->cs_local_opts[i].odt_rd_cfg = 3;
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popts->cs_local_opts[i].odt_wr_cfg = 3;
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}
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}
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}
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->twoT_en = 0;
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}
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pbsp++;
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Enable on-die termination.
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* From the Micron Technical Node TN-41-04, RTT_Nom should typically
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* be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
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* is handled in the Freescale DDR3 driver. Set RTT_Nom here.
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*/
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popts->rtt_override = 1;
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popts->rtt_override_value = 3;
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}
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@@ -0,0 +1,54 @@
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/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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#endif
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#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
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#endif
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#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
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SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@@ -0,0 +1,98 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* W**G* - NOR flashes */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 0, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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/* *I*G* - NAND flash */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_1M, 1),
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/* **M** - Boot page for secondary processors */
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SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 3, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_PCIE1
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1G, 1),
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#endif
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#ifdef CONFIG_PCIE2
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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#endif
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#ifdef CONFIG_PCIE3
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256M, 1),
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#endif
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#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_64M, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@@ -0,0 +1,107 @@
|
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/*
|
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* Copyright 2010 Extreme Engineering Solutions, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cache.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <pca953x.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void ft_board_pci_setup(void *blob, bd_t *bd);
|
||||
|
||||
static void flash_cs_fixup(void)
|
||||
{
|
||||
int flash_sel;
|
||||
|
||||
/*
|
||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
||||
* flash. Swapping chip selects presents user with a common memory
|
||||
* map regardless of which flash was booted from.
|
||||
*/
|
||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
||||
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
|
||||
|
||||
if (flash_sel) {
|
||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
||||
|
||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/* Initialize PCA9557 devices */
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
|
||||
|
||||
/*
|
||||
* Remap NOR flash region to caching-inhibited
|
||||
* so that flash can be erased/programmed properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* Invalidate existing TLB entry for NOR flash */
|
||||
disable_tlb(0);
|
||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
flash_cs_fixup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
ft_board_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
|
||||
|
||||
void board_lmb_reserve(struct lmb *lmb)
|
||||
{
|
||||
cpu_mp_lmb_reserve(lmb);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user