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miiphy: convert to linux/mii.h

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The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2010-12-23 15:40:12 -05:00
committed by Wolfgang Denk
parent 4ffeab2cc0
commit 8ef583a035
45 changed files with 360 additions and 457 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/qe/uec_phy.c
+34 -34
View File
@@ -242,7 +242,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info)
advertise = mii_info->advertising;
/* Setup standard advertisement */
adv = phy_read (mii_info, PHY_ANAR);
adv = phy_read (mii_info, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
@@ -252,7 +252,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
phy_write (mii_info, PHY_ANAR, adv);
phy_write (mii_info, MII_ADVERTISE, adv);
}
static void genmii_setup_forced (struct uec_mii_info *mii_info)
@@ -260,24 +260,24 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
u16 ctrl;
u32 features = mii_info->phyinfo->features;
ctrl = phy_read (mii_info, PHY_BMCR);
ctrl = phy_read (mii_info, MII_BMCR);
ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
ctrl |= PHY_BMCR_RESET;
ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
BMCR_SPEED1000 | BMCR_ANENABLE);
ctrl |= BMCR_RESET;
switch (mii_info->speed) {
case SPEED_1000:
if (features & (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full)) {
ctrl |= PHY_BMCR_1000_MBPS;
ctrl |= BMCR_SPEED1000;
break;
}
mii_info->speed = SPEED_100;
case SPEED_100:
if (features & (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full)) {
ctrl |= PHY_BMCR_100_MBPS;
ctrl |= BMCR_SPEED100;
break;
}
mii_info->speed = SPEED_10;
@@ -290,7 +290,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
break;
}
phy_write (mii_info, PHY_BMCR, ctrl);
phy_write (mii_info, MII_BMCR, ctrl);
}
/* Enable and Restart Autonegotiation */
@@ -298,9 +298,9 @@ static void genmii_restart_aneg (struct uec_mii_info *mii_info)
{
u16 ctl;
ctl = phy_read (mii_info, PHY_BMCR);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
phy_write (mii_info, PHY_BMCR, ctl);
ctl = phy_read (mii_info, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write (mii_info, MII_BMCR, ctl);
}
static int gbit_config_aneg (struct uec_mii_info *mii_info)
@@ -335,7 +335,7 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
/* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation */
phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
phy_write (mii_info, MII_BMCR, BMCR_RESET);
phy_write (mii_info, 0x1d, 0x1f);
phy_write (mii_info, 0x1e, 0x200c);
@@ -373,18 +373,18 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
u16 status;
/* Status is read once to clear old link state */
phy_read (mii_info, PHY_BMSR);
phy_read (mii_info, MII_BMSR);
/*
* Wait if the link is up, and autonegotiation is in progress
* (ie - we're capable and it's not done)
*/
status = phy_read(mii_info, PHY_BMSR);
if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
&& !(status & PHY_BMSR_AUTN_COMP)) {
status = phy_read(mii_info, MII_BMSR);
if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
&& !(status & BMSR_ANEGCOMPLETE)) {
int i = 0;
while (!(status & PHY_BMSR_AUTN_COMP)) {
while (!(status & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
@@ -395,11 +395,11 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
i++;
udelay(1000); /* 1 ms */
status = phy_read(mii_info, PHY_BMSR);
status = phy_read(mii_info, MII_BMSR);
}
mii_info->link = 1;
} else {
if (status & PHY_BMSR_LS)
if (status & BMSR_LSTATUS)
mii_info->link = 1;
else
mii_info->link = 0;
@@ -429,13 +429,13 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
else
mii_info->duplex = DUPLEX_HALF;
} else {
status = phy_read(mii_info, PHY_ANLPAR);
status = phy_read(mii_info, MII_LPA);
if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
if (status & (LPA_10FULL | LPA_100FULL))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
if (status & (LPA_100FULL | LPA_100HALF))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
@@ -463,8 +463,8 @@ static int bcm_init(struct uec_mii_info *mii_info)
/* Wait for aneg to complete. */
do
val = phy_read(mii_info, PHY_BMSR);
while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
val = phy_read(mii_info, MII_BMSR);
while (--cnt && !(val & BMSR_ANEGCOMPLETE));
/* Set RDX clk delay. */
phy_write(mii_info, 0x18, 0x7 | (7 << 12));
@@ -511,7 +511,7 @@ static int marvell_init(struct uec_mii_info *mii_info)
temp |= MII_M1111_HWCFG_MODE_RGMII;
phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
phy_write(mii_info, MII_BMCR, BMCR_RESET);
}
return 0;
@@ -582,11 +582,11 @@ static int marvell_config_intr (struct uec_mii_info *mii_info)
static int dm9161_init (struct uec_mii_info *mii_info)
{
/* Reset the PHY */
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
PHY_BMCR_RESET);
phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) |
BMCR_RESET);
/* PHY and MAC connect */
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
~PHY_BMCR_ISO);
phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) &
~BMCR_ISOLATE);
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
@@ -825,11 +825,11 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
struct phy_info *theInfo = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = phy_read (mii_info, PHY_PHYIDR1);
phy_reg = phy_read (mii_info, MII_PHYSID1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = phy_read (mii_info, PHY_PHYIDR2);
phy_reg = phy_read (mii_info, MII_PHYSID2);
phy_ID |= (phy_reg & 0xffff);
/* loop through all the known PHY types, and find one that */
@@ -900,8 +900,8 @@ void marvell_phy_interface_mode (struct eth_device *dev,
/* handle 88e1111 rev.B2 erratum 5.6 */
if (mii_info->autoneg) {
status = phy_read (mii_info, PHY_BMCR);
phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
status = phy_read (mii_info, MII_BMCR);
phy_write (mii_info, MII_BMCR, status | BMCR_ANENABLE);
}
/* now the B2 will correctly report autoneg completion status */
}
drivers/qe/uec_phy.h
-18
View File
@@ -169,24 +169,6 @@
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_RESV 0x1c00 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
/* Information about the PHY type */