sunxi: display: add simplefb support for V3s SoC

V3s SoC features a DE2 composer.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -449,9 +449,13 @@ struct sunxi_ccm_reg {
 /* CCM bits common to all Display Engine 2.0 clock ctrl regs */
 #define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
 #define CCM_DE2_CTRL_PLL_MASK		(3 << 24)
+#ifndef CONFIG_MACH_SUN8I_V3S
 #define CCM_DE2_CTRL_PLL6_2X		(0 << 24)
 #define CCM_DE2_CTRL_PLL10		(1 << 24)
-#define CCM_DE2_CTRL_PLL3		(1 << 24) /* for V3s */
+#else
+#define CCM_DE2_CTRL_PLL3		(0 << 24) /* for V3s */
+#define CCM_DE2_CTRL_PLL6_2X		(2 << 24)
+#endif
 #define CCM_DE2_CTRL_GATE		(1 << 31)
 
 /* CCU security switch, H3 only */
@@ -470,6 +474,7 @@ void clock_set_mipi_pll(unsigned int hz);
 unsigned int clock_get_pll3(void);
 unsigned int clock_get_pll6(void);
 unsigned int clock_get_mipi_pll(void);
+void clock_set_de2_mod_clock(u32 *clk_cfg, unsigned int hz);
 #endif
 
 #endif /* _SUNXI_CLOCK_SUN6I_H */

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h

@@ -18,6 +18,8 @@
 #define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
 #define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
 
+#define SUNXI_DE2_BASE			0x01000000
+
 #ifdef CONFIG_MACH_SUN8I_A83T
 #define SUNXI_CPUCFG_BASE		0x01700000
 #endif

arch/arm/include/asm/arch-sunxi/display.h

@@ -157,6 +157,89 @@ struct sunxi_de_be_reg {
 	u32 output_color_coef[12];	/* 0x9d0 */
 };
 
+/*
+ * The following structures are for DE2.
+ * DE2 is a new generation of "composer" in some new Allwinner SoCs, such as
+ * A83T, H3, V3s, A64.
+ */
+
+/* internal clock settings */
+struct de_clk {
+	u32 gate_cfg;
+	u32 bus_cfg;
+	u32 rst_cfg;
+	u32 div_cfg;
+	u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+	u32 ctl;
+	u32 status;
+	u32 dbuff;
+	u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+	u32 fcolor_ctl;			/* 00 */
+	struct {
+		u32 fcolor;
+		u32 insize;
+		u32 offset;
+		u32 dum;
+	} attr[4];
+	u32 dum0[15];			/* (end of clear offset) */
+	u32 route;			/* 80 */
+	u32 premultiply;
+	u32 bkcolor;
+	u32 output_size;
+	u32 bld_mode[4];
+	u32 dum1[4];
+	u32 ck_ctl;			/* b0 */
+	u32 ck_cfg;
+	u32 dum2[2];
+	u32 ck_max[4];			/* c0 */
+	u32 dum3[4];
+	u32 ck_min[4];			/* e0 */
+	u32 dum4[3];
+	u32 out_ctl;			/* fc */
+};
+
+/* VI channel */
+struct de_vi {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch[3];
+		u32 top_laddr[3];
+		u32 bot_laddr[3];
+	} cfg[4];
+	u32 fcolor[4];			/* c0 */
+	u32 top_haddr[3];		/* d0 */
+	u32 bot_haddr[3];		/* dc */
+	u32 ovl_size[2];		/* e8 */
+	u32 hori[2];			/* f0 */
+	u32 vert[2];			/* f8 */
+};
+
+struct de_ui {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch;
+		u32 top_laddr;
+		u32 bot_laddr;
+		u32 fcolor;
+		u32 dum;
+	} cfg[4];			/* 00 */
+	u32 top_haddr;			/* 80 */
+	u32 bot_haddr;
+	u32 ovl_size;			/* 88 */
+};
+
 struct sunxi_lcdc_reg {
 	u32 ctrl;			/* 0x00 */
 	u32 int0;			/* 0x04 */
@@ -346,6 +429,42 @@ struct sunxi_tve_reg {
 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888	(0x09 << 8)
 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE	1
 
+/*
+ * DE2 register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE			(u8 *)(SUNXI_DE2_BASE + 0x100000)
+
+#define SUNXI_DE2_MUX_GLB_REGS			0x00000
+#define SUNXI_DE2_MUX_BLD_REGS			0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS			0x02000
+#define	SUNXI_DE2_MUX_CHAN_SZ			0x1000
+#define SUNXI_DE2_MUX_VSU_REGS			0x20000
+#define SUNXI_DE2_MUX_GSU1_REGS			0x30000
+#define SUNXI_DE2_MUX_GSU2_REGS			0x40000
+#define SUNXI_DE2_MUX_GSU3_REGS			0x50000
+#define SUNXI_DE2_MUX_FCE_REGS			0xa0000
+#define SUNXI_DE2_MUX_BWS_REGS			0xa2000
+#define SUNXI_DE2_MUX_LTI_REGS			0xa4000
+#define SUNXI_DE2_MUX_PEAK_REGS			0xa6000
+#define SUNXI_DE2_MUX_ASE_REGS			0xa8000
+#define SUNXI_DE2_MUX_FCC_REGS			0xaa000
+#define SUNXI_DE2_MUX_DCSC_REGS			0xb0000
+
+#define SUNXI_DE2_FORMAT_ARGB_8888		0
+#define SUNXI_DE2_FORMAT_BGRA_8888		3
+#define SUNXI_DE2_FORMAT_XRGB_8888		4
+#define SUNXI_DE2_FORMAT_RGB_888		8
+#define SUNXI_DE2_FORMAT_BGR_888		9
+
+#define SUNXI_DE2_MUX_GLB_CTL_RT_EN		(1 << 0)
+
+#define SUNXI_DE2_UI_CFG_ATTR_EN		(1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_ALPMOD(m)		((m & 3) << 1)
+#define SUNXI_DE2_UI_CFG_ATTR_FMT(f)		((f & 0xf) << 8)
+#define SUNXI_DE2_UI_CFG_ATTR_ALPHA(a)		((a & 0xff) << 24)
+
+#define SUNXI_DE2_WH(w, h)			(((h - 1) << 16) | (w - 1))
+
 /*
  * LCDC register constants.
  */

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -151,6 +151,7 @@ enum sunxi_gpio_number {
 #define SUN8I_H3_GPA_UART0	2
 
 #define SUN4I_GPB_PWM		2
+#define SUN8I_V3S_GPB_PWM	2
 #define SUN4I_GPB_TWI0		2
 #define SUN4I_GPB_TWI1		2
 #define SUN5I_GPB_TWI1		2
@@ -176,6 +177,7 @@ enum sunxi_gpio_number {
 
 #define SUN5I_GPE_SDC2		3
 #define SUN8I_GPE_TWI2		3
+#define SUN8I_V3S_GPE_LCD	3
 
 #define SUNXI_GPF_SDC0		2
 #define SUNXI_GPF_UART0		4

arch/arm/include/asm/arch-sunxi/pwm.h

@@ -31,4 +31,9 @@
 #define SUNXI_PWM_MUX			SUN8I_GPH_PWM
 #endif
 
+#if defined CONFIG_MACH_SUN8I_V3S
+#define SUNXI_PWM_PIN0			SUNXI_GPB(4)
+#define SUNXI_PWM_MUX			SUN8I_V3S_GPB_PWM
+#endif
+
 #endif

arch/arm/mach-sunxi/clock_sun6i.c

@@ -317,3 +317,15 @@ void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 	       clk_cfg);
 }
+
+void clock_set_de2_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+	int pll = clock_get_pll6() * 2;
+	int div = 1;
+
+	while ((pll / div) > hz)
+		div++;
+
+	writel(CCM_DE2_CTRL_GATE | CCM_DE2_CTRL_PLL6_2X | CCM_DE2_CTRL_M(div),
+	       clk_cfg);
+}