From 7e47c8101dbe36095dcbc8a700a4ca6448f4383b Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 21 May 2017 12:32:02 +0800 Subject: [PATCH] sunxi: add SPI0 node for V3s DTSI Allwinner V3s SoC has a SPI controller which is the same as the controllers in H3 SoC. Add a device tree node for it, so that it can be usable. Signed-off-by: Icenowy Zheng --- arch/arm/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index ebefc0fefe..8ab30219d3 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -221,6 +221,11 @@ drive-strength = <30>; bias-pull-up; }; + + spi0_pins: spi0 { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; }; timer@01c20c00 { @@ -270,6 +275,20 @@ status = "disabled"; }; + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>,