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armv8: LS2080A: Consolidate LS2080A and LS2085A

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LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
York Sun
2016-04-04 11:41:26 -07:00
parent 2a55583998
commit 3c1d218a1d
36 changed files with 115 additions and 248 deletions
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arch/arm/cpu/armv8/fsl-layerscape/soc.c
+25 -1
View File
@@ -18,7 +18,31 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has DP_DDR */
if (SVR_SOC_VER(svr) == SVR_LS2085)
return true;
return false;
}
bool soc_has_aiop(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
if (SVR_SOC_VER(svr) == SVR_LS2085)
return true;
return false;
}
#ifdef CONFIG_LS2080A
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.