nearology/u-boot
1
0
Fork 0
Code Actions Activity

powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081

Browse Source 
Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun
2016-11-21 12:54:19 -08:00
parent 01671e668b
commit 0f3d80e993
27 changed files with 51 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/powerpc/cpu/mpc85xx/Kconfig
+9
View File
@@ -244,16 +244,19 @@ config TARGET_T1042RDB_PI
config TARGET_T2080QDS
bool "Support T2080QDS"
select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T2080RDB
bool "Support T2080RDB"
select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T2081QDS
bool "Support T2081QDS"
select ARCH_T2081
select SUPPORT_SPL
select PHYS_64BIT
@@ -400,6 +403,12 @@ config ARCH_T1040
config ARCH_T1042
bool
config ARCH_T2080
bool
config ARCH_T2081
bool
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
arch/powerpc/cpu/mpc85xx/Makefile
+4 -4
View File
@@ -55,8 +55,8 @@ obj-$(CONFIG_PPC_T1020) += t1040_ids.o
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
@@ -98,8 +98,8 @@ obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o
arch/powerpc/cpu/mpc85xx/fdt.c
+2 -2
View File
@@ -511,7 +511,7 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \
defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
void fdt_fixup_dma3(void *blob)
{
@@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob)
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
arch/powerpc/cpu/mpc85xx/speed.c
+5 -5
View File
@@ -131,8 +131,8 @@ void get_sys_info(sys_info_t *sys_info)
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
defined(CONFIG_PPC_T2081)
defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
defined(CONFIG_ARCH_T2081)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@@ -203,7 +203,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
@@ -456,7 +456,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define ESDHC_CLK_SEL 0x00000007
#define ESDHC_CLK_SHIFT 0
#define ESDHC_CLK_RCWSR 15
@@ -480,7 +480,7 @@ void get_sys_info(sys_info_t *sys_info)
case 4:
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
break;
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
case 5:
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
break;
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+2 -2
View File
@@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{}
};
#ifndef CONFIG_PPC_T2081
#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
#ifndef CONFIG_PPC_T2081
#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
arch/powerpc/include/asm/config_mpc85xx.h
+3 -3
View File
@@ -779,7 +779,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -794,7 +794,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCI_VER_3_X
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
@@ -802,7 +802,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
arch/powerpc/include/asm/immap_85xx.h
+2 -2
View File
@@ -1812,7 +1812,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
@@ -1885,7 +1885,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000